Configuring Keyword Alignment Rules

There are several rules that enforce alignment for a group of lines based on the keywords such as ‘after’, ‘<=’ etc. Some of the configurations are available in all keyword alignment rules, while others are rule specific.

There are several options to these rules:

Note

Some options are rule dependent.

Option

Values

Default

Description

compact_alignment

yes, no

yes

  • yes = Align to left most column.

  • no = Align to right most column.

blank_line_ends_group

yes, no

yes

  • yes = stop if a blank line is encountered.

  • no = continue if a blank line is encountered.

comment_line_ends_group

yes, no

yes

  • yes = stop if a blank line is encountered.

  • no = continue if a blank line is encountered.

separate_generic_port_alignment

yes, no

yes

  • yes = stop if port keyword detected.

  • no = continue if port keyword detected.

if_control_statements_ends_group

yes, no

yes

  • yes = stop when an if structure keyword is encountered.

  • no = continue when an if structure keyword is encountered.

case_control_statements_ends_group

yes, no, break_on_case_or_end_case

yes

  • yes = stop when a case control keyword is encountered.

  • no = continue when a case control keyword is encountered.

  • break_on_case_or_end_case = Stop alignment if case or end case is encountered.

generate_statements_ends_group

yes, no

yes

  • yes = stop when a generate statement keyword is encountered.

  • no = continue when a generate statement keyword is encountered.

loop_control_generic_port_alignment

yes, no

yes

  • yes = stop when a loop control statement keyword is encountered.

  • no = continue when a loop control statement keyword is encountered.

include_type_is_keyword

yes, no

no

  • yes = align type is keyword with colons.

  • no = ignore type is keywords for alignment.

aggregate_parens_ends_group

yes, no

no

  • yes = stop when an aggregate parenthesis is encountered.

  • no = continue when an aggregate parenthesis is encountered.

ignore_single_line_aggregates

yes, no

no

  • yes = ignore aggregates which are on a single line.

  • no = include aggregates which are on a single line.

align_to

keyword, current_indent

keyword

  • keyword = align to the keyword specified in rule

  • current_indent = align to the current indent level

This is an example of how to configure these options.

rule :
  process_031:
     compact_alignment: 'yes'
     blank_line_ends_group: 'yes'
     comment_line_ends_group : 'yes'
     separate_generic_port_alignment: 'yes'
     if_control_statements_ends_group: 'yes'
     case_control_statements_ends_group: 'yes'
     generate_statements_ends_group: 'yes'
     loop_control_statements_ends_group: 'yes'
     aggregate_parens_ends_group: 'yes'
     ignore_single_line_aggregates: 'yes'
     include_type_is_keyword: 'no'

Example: compact_alignment set to yes

Enforces single space before alignment keyword in the line with the longest part before the keyword.

Violation

signal sig_short   : std_logic;
signal sig_very_long      : std_logic;

Fix

signal sig_short     : std_logic;
signal sig_very_long : std_logic;

Example: compact_alignment set to no

Aligns to right most instance of keyword.

Violation

signal sig_short   : std_logic;
signal sig_very_long      : std_logic;

Fix

signal sig_short          : std_logic;
signal sig_very_long      : std_logic;

Example: blank_line_ends_group set to yes

Any blank line encountered in the VHDL file ends the group of lines that should be aligned and starts new group.

Violation

signal wr_en : std_logic;
signal rd_en   : std_logic;

constant c_short_period : time;
constant c_long_period : time;

Fix

signal wr_en   : std_logic;
signal rd_en   : std_logic;

constant c_short_period : time;
constant c_long_period  : time;

Example: blank_line_ends_group set to no

Any blank line encountered in the VHDL file will not end the group of lines that should be aligned.

Violation

signal wr_en : std_logic;
signal rd_en   : std_logic;

constant c_short_period : time;
constant c_long_period : time;

Fix

signal wr_en            : std_logic;
signal rd_en            : std_logic;

constant c_short_period : time;
constant c_long_period  : time;

Example: comment_line_ends_group set to yes

Any comment line in the VHDL file ends the group of lines that should be aligned and starts new group.

Violation

port (
    sclk_i : in std_logic;
    pclk_i : in std_logic;
    rst_i : in std_logic;
    ---- serial interface ----
    spi_ssel_o : out std_logic;
    spi_sck_o : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in std_logic
);

Fix

port (
    sclk_i : in std_logic;
    pclk_i : in std_logic;
    rst_i  : in std_logic;
    ---- serial interface ----
    spi_ssel_o : out std_logic;
    spi_sck_o  : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in std_logic
);

Example: comment_line_ends_group set to no

Any comment line in the VHDL file will not end the group of lines that should be aligned and starts new group.

Violation

port (
    sclk_i : in std_logic;
    pclk_i : in std_logic;
    rst_i : in std_logic;
    ---- serial interface ----
    spi_ssel_o : out std_logic;
    spi_sck_o : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in std_logic
);

Fix

port (
    sclk_i     : in std_logic;
    pclk_i     : in std_logic;
    rst_i      : in std_logic;
    ---- serial interface ----
    spi_ssel_o : out std_logic;
    spi_sck_o  : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in std_logic
);

Example: separate_generic_port_alignment set to yes

Alignment within the generic declarative/mapping part is separated from alignment within the port declarative/mapping part.

Violation

generic (
    g_width : positive;
    g_output_delay : positive
);
port (
    clk_i : in std_logic;
    data_i : in std_logic;
    data_o : in std_logic
);

Fix

generic (
    g_width        : positive;
    g_output_delay : positive
);
port (
    clk_i  : in std_logic;
    data_i : in std_logic;
    data_o : in std_logic
);

Example: separate_generic_port_alignment set to no

Alignment within the generic declarative/mapping part is the same as the alignment within the port declarative/mapping part.

Violation

generic (
    g_width : positive;
    g_output_delay : positive
);
port (
    clk_i : in std_logic;
    data_i : in std_logic;
    data_o : in std_logic
);

Fix

generic (
    g_width        : positive;
    g_output_delay : positive
);
port (
    clk_i          : in std_logic;
    data_i         : in std_logic;
    data_o         : in std_logic
);

Example: if_control_statements_ends_group set to yes

Any line with if control statement ends the group of lines that should be aligned and starts new group.

Violation

if condition = '1' then
    data_valid <= '1';
    data <= '1';
else
    data_valid <= '0';
    hold_transmission <= '1';
end if;

Fix

if condition = '1' then
    data_valid <= '1';
    data       <= '1';
else
    data_valid        <= '0';
    hold_transmission <= '1';
end if;

Example: if_control_statements_ends_group set to no

Any line with if control statement does not end the group of lines that should be aligned and starts new group.

Violation

if condition = '1' then
    data_valid <= '1';
    data <= '1';
else
    data_valid <= '0';
    hold_transmission <= '1';
end if;

Fix

if condition = '1' then
    data_valid        <= '1';
    data              <= '1';
else
    data_valid        <= '0';
    hold_transmission <= '1';
end if;

Example: case_control_statements_ends_group set to yes

Any line with case control statements (case, when or end case) ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
case A is
    when A =>
        X <= F;
        XY <= G;
        XYZ <= H;
    when B =>
        a <= I;
        ab <= h;
        c <= a;
    when others =>
      null;
end case;
data_valid_after       <= '1';

Fix

data_valid_before <= '1';
case A is
    when A =>
        X   <= F;
        XY  <= G;
        XYZ <= H;
    when B =>
        a  <= I;
        ab <= h;
        c  <= a;
    when others =>
        null;
end case;
data_valid_after <= '1';

Example: case_control_statements_ends_group set to no

No line with case control statements ends the group of lines that should be aligned and starts a group.

Violation

data_valid_before    <= '1';
case A is
    when A =>
        X <= F;
        XY <= G;
        XYZ <= H;
    when B =>
        a <= I;
        ab <= h;
        c <= a;
    when others =>
      null;
end case;
data_valid_after       <= '1';

Fix

data_valid_before <= '1';
case A is
    when A =>
        X         <= F;
        XY        <= G;
        XYZ       <= H;
    when B =>
        a         <= I;
        ab        <= h;
        c         <= a;
    when others =>
        null;
end case;
data_valid_after  <= '1';

Example: case_control_statements_ends_group set to break_on_case_or_end_case

Any line with case or end case ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
case A is
    when A =>
        X <= F;
        XY <= G;
        XYZ <= H;
    when B =>
        a <= I;
        ab <= h;
        c <= a;
    when others =>
      null;
end case;
data_valid_after       <= '1';

Fix

data_valid_before <= '1';
case A is
    when A =>
        X   <= F;
        XY  <= G;
        XYZ <= H;
    when B =>
        a   <= I;
        ab  <= h;
        c   <= a;
    when others =>
        null;
end case;
data_valid_after <= '1';

Example: generate_statements_ends_group set to yes

Any line with generate statement keywords ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
generate_label : if G_ENABLE = '1' generate
    data_valid <= '0';
    hold_transmission <= '1';
end generate;
data_valid_after       <= '1';

Fix

data_valid_before <= '1';
generate_label : if G_ENABLE = '1' generate
    data_valid        <= '0';
    hold_transmission <= '1';
end generate;
data_valid_after <= '1';

Example: generate_statements_ends_group set to no

No line with generate statement keywords ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
generate_label : if G_ENABLE = '1' generate
    data_valid <= '0';
    hold_transmission <= '1';
end generate;
data_valid_after       <= '1';

Fix

data_valid_before     <= '1';
generate_label : if G_ENABLE = '1' generate
    data_valid        <= '0';
    hold_transmission <= '1';
end generate;
data_valid_after      <= '1';

Example: loop_control_generic_port_alignment set to yes

Any line with loop control statement (including for and while loops) ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
for index in 4 to 23 loop
    data_valid <= '0';
    hold_transmission <= '1';
end loop;
data_valid_after       <= '1';

Fix

data_valid_before <= '1';
for index in 4 to 23 loop
    data_valid        <= '0';
    hold_transmission <= '1';
end loop;
data_valid_after <= '1';

Example: loop_control_generic_port_alignment set to no

No line with loop control statement (including for and while loops) ends the group of lines that should be aligned and starts new group.

Violation

data_valid_before    <= '1';
for index in 4 to 23 loop
    data_valid <= '0';
    hold_transmission <= '1';
end loop;
data_valid_after       <= '1';

Fix

data_valid_before     <= '1';
for index in 4 to 23 loop
    data_valid        <= '0';
    hold_transmission <= '1';
end loop;
data_valid_after      <= '1';

Example: include_type_is_keyword set to yes

Any blank line encountered in the VHDL file ends the group of lines that should be aligned and starts new group.

Violation

signal wr_en : std_logic;
signal rd_en   : std_logic;
type sm is (idle, read, write);
constant c_short_period : time;
constant c_long_period : time;

Fix

signal wr_en            : std_logic;
signal rd_en            : std_logic;
type sm                 is (idle, read, write);
constant c_short_period : time;
constant c_long_period  : time;

Example: include_type_is_keyword set to no

Any blank line encountered in the VHDL file will not end the group of lines that should be aligned.

Violation

signal wr_en : std_logic;
signal rd_en   : std_logic;
type sm is (idle, read, write);
constant c_short_period : time;
constant c_long_period : time;

Fix

signal wr_en            : std_logic;
signal rd_en            : std_logic;
type sm is (idle, read, write);
constant c_short_period : time;
constant c_long_period  : time;

Example: aggregate_parens_ends_group set to yes

Any aggregate parenthesis encountered in the VHDL file will end the group of lines that should be aligned.

Violation

constant my_constant : my_type := (
  ENUM_1   => (
    A      => 1,
    B      => 2,
    C      => 3
  ),
  ENUM_234 => (
    AA     => 1,
    BB     => 2,
    CC     => 3
  )
);

Fix

constant my_constant : my_type := (
  ENUM_1 => (
    A => 1,
    B => 2,
    C => 3
  ),
  ENUM_234 => (
    AA => 1,
    BB => 2,
    CC => 3
  )
);

Example: aggregate_parens_ends_group set to no

Any aggregate parenthesis encountered in the VHDL file will not end the group of lines that should be aligned.

Violation

constant my_constant : my_type := (
  ENUM_1 => (
    A => 1,
    B => 2,
    C => 3
  ),
  ENUM_234 => (
    AA => 1,
    BB => 2,
    CC => 3
  )
);

Fix

constant my_constant : my_type := (
  ENUM_1   => (
    A      => 1,
    B      => 2,
    C      => 3
  ),
  ENUM_234 => (
    AA     => 1,
    BB     => 2,
    CC     => 3
  )
);

Example: aggregate_parens_ends_group set to yes and ignore_single_line_aggregates set to yes

Any aggregate which is fully contained on a single line, including parenthesis, will not be considered defining a group. In the example below, the others aggregates are ignored which will allow the ENUM_1 assignment and ENUM_234 assignment to be aligned.

Violation

constant my_constant : my_type := (
  ENUM_1 => (others => '0'),
  ENUM_234 => (others => '1')
);

Fix

constant my_constant : my_type := (
  ENUM_1   => (others => '0'),
  ENUM_234 => (others => '1')
);

Example: align_to set to current_indent

For example in rule process_028 the close parenthesis will be aligned with the process keyword.

Violation

process (rd_en, wr_en,
         wr_valid, rd_valid
        )

Fix

process (rd_en, wr_en,
         wr_valid, rd_valid
)

Example: align_to set to keyword

For example in rule process_028 the close parenthesis will be aligned with the open parenthesis.

Violation

process (rd_en, wr_en,
         wr_valid, rd_valid
)

Fix

process (rd_en, wr_en,
         wr_valid, rd_valid
        )

Rules Enforcing Keyword Alignment