Configuring Keyword Alignment Rules
There are several rules that enforce alignment for a group of lines based on the keywords such as ‘after’, ‘<=’ etc. Some of the configurations are available in all keyword alignment rules, while others are rule specific.
Common Keyword Alignment Configuration
Following configuration options can be independently changed for each of the keyword alignment rules.
compact_alignment
- if set toTrue
it enforces single space before alignment keyword in the line with the longest part before the keyword. Otherwise the alignment occurs to the keyword maximum column. By default set toTrue
.Violation
signal sig_short : std_logic; signal sig_very_long : std_logic;
Fix (compact_alignment = True)
signal sig_short : std_logic; signal sig_very_long : std_logic;
Fix (compact_alignment = False)
signal sig_short : std_logic; signal sig_very_long : std_logic;
blank_line_ends_group
- if set toTrue
any blank line encountered in the VHDL file ends the group of lines that should be aligned and starts new group. By default set toTrue
.Violation
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Fix (blank_line_ends_group = True)
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Fix (blank_line_ends_group = False)
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
comment_line_ends_group
- if set toTrue
any purely comment line in the VHDL file ends the group of lines that should be aligned and starts new group. By default set toTrue
.Violation
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );
Fix (comment_line_ends_group = True)
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );
Fix (comment_line_ends_group = False)
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );
Note
As all keyword alignment rules have above configurations they are not mentioned in the documentation for each rule.
Rule Specific Keyword Alignment Configuration
separate_generic_port_alignment
- if set toTrue
alignment within the generic declarative/mapping part is separated from alignment within the port declarative/mapping part. By default set toTrue
.Violation
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );
Fix (separate_generic_port_alignment = True)
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );
Fix (separate_generic_port_alignment = False)
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );
if_control_statements_ends_group
- if set toTrue
any line with if control statement ends the group of lines that should be aligned and starts new group. By default set toTrue
.Violation
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;
Fix (if_control_statements_ends_group = True)
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;
Fix (if_control_statements_ends_group = False)
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;
case_control_statements_ends_group
- if set toTrue
, any line with case control statements (case
,when
orend case
) ends the group of lines that should be aligned and starts new group. If set toFalse
, no line with case control statements ends the group of lines that should be aligned and starts a group. If set tobreak_on_case_or_end_case
, any line withcase
orend case
ends the group of lines that should be aligned and starts new group. By default set toTrue
.Violation
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
Fix (case_control_statements_ends_group = True)
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
Fix (case_control_statements_ends_group = False)
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
Fix (case_control_statements_ends_group = break_on_case_or_end_case)
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
generate_statements_ends_group
- if set toTrue
any line with generate statement keywords ends the group of lines that should be aligned and starts new group. By default set toFalse
.Violation
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';
Fix (generate_statements_ends_group = True)
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';
Fix (generate_statements_ends_group = False)
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';
loop_control_statements_ends_group
- if set toTrue
any line with loop control statement (including for and while loops) ends the group of lines that should be aligned and starts new group. By default set toFalse
.Violation
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';
Fix (loop_control_statements_ends_group = True)
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';
Fix (loop_control_statements_ends_group = False)
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';
no_alignment
- if set toTrue
the keyword will be forced to the left. By default set toFalse
.Violation
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Fix
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Note
If given keyword alignment rule has any of the above keyword alignment specific configuration, then it is explicitly noted in the documentation of this rule.
The default value for each of these case rules can be overridden using a configuration.
Rules Enforcing Keyword Alignment
- after_002
- architecture_026
- architecture_027
- architecture_400
- block_401
- block_402
- case_generate_statement_400
- component_017
- component_020
- concurrent_006
- concurrent_008
- concurrent_400
- declarative_part_400
- entity_017
- entity_018
- entity_020
- function_012
- generate_401
- generate_403
- generate_405
- instantiation_010
- instantiation_029
- package_400
- package_401
- package_402
- package_body_401
- package_body_402
- procedure_401
- procedure_410
- procedure_411
- procedure_call_401
- process_031
- process_033
- process_034
- process_035
- process_400
- process_401
- sequential_400
- subprogram_body_400
- subprogram_body_401
- type_400