Instantiation Rules

instantiation_001

phase_4 error indent

This rule checks for the proper indentation of instantiations.

Violation

   U_FIFO : FIFO
port map (
         WR_EN    => wr_en,
 RD_EN    => rd_en,
       OVERFLOW => overflow
              );

Fix

U_FIFO : FIFO
  port map (
    WR_EN    => wr_en,
    RD_EN    => rd_en,
    OVERFLOW => overflow
  );

instantiation_002

phase_2 error whitespace

This rule checks for a single space after the colon.

Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..

Violation

U_FIFO :FIFO

Fix

U_FIFO : FIFO

instantiation_003

phase_2 error whitespace

This rule checks for a single space before the colon.

Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..

Violation

U_FIFO: FIFO

Fix

U_FIFO : FIFO

instantiation_004

phase_3 error blank_line

This rule checks for blank lines or comments above the instantiation.

Refer to Configuring Previous Line Rules for more information.

The default style is no_code.

Violation

WR_EN <= '1';
U_FIFO : FIFO

-- Instantiate another FIFO
U_FIFO2 : FIFO

Fix

WR_EN <= '1';

U_FIFO : FIFO

-- Instantiate another FIFO
U_FIFO2 : FIFO

instantiation_005

phase_1 error structure

This rule checks the port map keywords are on their own line.

Violation

U_FIFO : FIFO port map (

Fix

U_FIFO : FIFO
  port map (

instantiation_006

This rule has been renamed to port_map_001.

instantiation_007

This rule has been renamed to port_map_004.

instantiation_008

phase_6 error case case_label

This rule checks the instance label has proper case.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

U_FIFO : fifo

Fix

u_fifo : fifo

instantiation_009

phase_6 error case case_name

This rule checks the component name has proper case.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

u_fifo : FIFO

Fix

u_fifo : fifo

instantiation_010

phase_5 error alignment

This rule checks the alignment of the => operator for each generic and port in the instantiation.

Following extra configurations are supported:

  • separate_generic_port_alignment.

Refer to Configuring Keyword Alignment Rules for information on changing the configurations.

Violation

U_FIFO : FIFO
  generic map (
    g_width => 8,
    g_delay    => 2
  )
  port map (
    wr_en => wr_en,
    rd_en => rd_en,
    overflow => overflow
  );

Fix

U_FIFO : FIFO
  generic map (
    g_width => 8,
    g_delay => 2
  )
  port map (
    wr_en    => wr_en,
    rd_en    => rd_en,
    overflow => overflow
  );

instantiation_011

This rule has been renamed to port_map_002.

instantiation_012

phase_1 error structure

This rule checks the instantiation declaration and the generic map keywords are not on the same line.

Violation

U_FIFO : FIFO generic map (

Fix

U_FIFO : FIFO
  generic map (

instantiation_013

This rule has been renamed to generic_map_001.

instantiation_014

This rule has been renamed to generic_map_004.

instantiation_016

This rule has been renamed to generic_map_002.

instantiation_017

This rule has been renamed to generic_map_005.

instantiation_018

This rule has been renamed to generic_map_006.

instantiation_019

phase_3 error blank_line

This rule checks for a blank line below the end of the instantiation declaration.

Refer to Configuring Blank Lines for more information.

Violation

U_FIFO : FIFO
  port map (
    WR_EN    => wr_en,
    RD_EN    => rd_en,
    OVERFLOW => overflow
  );
U_RAM : RAM

Fix

U_FIFO : FIFO
  port map (
    WR_EN    => wr_en,
    RD_EN    => rd_en,
    OVERFLOW => overflow
  );

U_RAM : RAM

instantiation_020

This rule has been renamed to port_map_005.

instantiation_021

This rule has been renamed to port_map_009.

instantiation_022

This rule has been renamed to port_map_007.

instantiation_023

phase_1 error structure

This rule checks for comments at the end of the port and generic assignments in instantiations. These comments represent additional maintainence. They will be out of sync with the entity at some point. Refer to the entity for port types, port directions and purpose.

Violation

WR_EN => w_wr_en;   -- out : std_logic
RD_EN => w_rd_en;   -- Reads data when asserted

Fix

WR_EN => w_wr_en;
RD_EN => w_rd_en;

instantiation_024

This rule has been split into:

instantiation_025

This rule has been renamed to port_map_003.

instantiation_026

This rule has been renamed to generic_map_003.

instantiation_027

phase_6 error case case_keyword

This rule checks the entity keyword has proper case in direct instantiations.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

INSTANCE_NAME : ENTITY library.ENTITY_NAME

Fix

INSTANCE_NAME : entity library.ENTITY_NAME

instantiation_028

phase_6 error case case_name

This rule checks the entity name has proper case in direct instantiations.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

instance_name : entity library.ENTITY_NAME

Fix

instance_name : entity library.entity_name

instantiation_029

phase_5 error alignment

This rule checks for alignment of inline comments in an instantiation.

Following extra configurations are supported:

  • separate_generic_port_alignment.

Refer to Configuring Keyword Alignment Rules for information on changing the configurations. Violation

Violation

wr_en    => write_enable,        -- Wrte enable
rd_en    => read_enable,    -- Read enable
overflow => overflow,         -- FIFO has overflowed

Fix

wr_en    => write_enable, -- Wrte enable
rd_en    => read_enable,  -- Read enable
overflow => overflow,     -- FIFO has overflowed

instantiation_030

This rule has been renamed to generic_map_007.

instantiation_031

phase_6 error case case_keyword

This rule checks the component keyword has proper case in component instantiations that use the component keyword.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

instance_name : COMPONENT entity_name

Fix

instance_name : component entity_name

instantiation_032

phase_2 error whitespace

This rule checks for a single space after the component keyword if it is used.

Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..

Violation

INSTANCE_NAME : component ENTITY_NAME
INSTANCE_NAME : component   ENTITY_NAME
INSTANCE_NAME : component  ENTITY_NAME

Fix

INSTANCE_NAME : component ENTITY_NAME
INSTANCE_NAME : component ENTITY_NAME
INSTANCE_NAME : component ENTITY_NAME

instantiation_033

phase_1 error structure structure_optional

This rule checks for the component keyword for a component instantiation.

Refer to Configuring Optional Items for more information.

Violation

INSTANCE_NAME : ENTITY_NAME

Fix

INSTANCE_NAME : component ENTITY_NAME

instantiation_034

phase_1 error structure

This rule checks for component versus direct instantiations.

Refer to Configuring Type of Instantiations for more information.

component instantiation

Note

This is the default configuration

Violation

U_FIFO : entity fifo_dsn.FIFO(RTL)

entity instantiation

Violation

U_FIFO : component FIFO

U_FIFO : FIFO

instantiation_035

phase_1 error structure

This rule checks the semicolon is not on its own line.

Violation

U_FIFO : FIFO
  port map (
    A => B,
    B => C)
  ;

Fix

U_FIFO : FIFO
  port map (
    A => B,
    B => C);

instantiation_600

phase_7 disabled error naming

This rule checks for valid suffixes on instantiation labels. The default suffix is _inst.

Refer to Configuring Prefix and Suffix Rules for more information.

Violation

fifo_32x2k : FIFO

Fix

fifo_32x2k_inst : FIFO

instantiation_601

phase_7 disabled error naming

This rule checks for valid prefixes on instantiation labels. The default prefix is inst_.

Refer to Configuring Prefix and Suffix Rules for more information.

Violation

fifo_32x2k : FIFO

Fix

inst_fifo_32x2k : FIFO