Architecture Rules¶
architecture_001¶
This rule checks for blank spaces before the architecture keyword.
Violation
architecture rtl of fifo is
begin
Fix
architecture rtl of fifo is
begin
architecture_002¶
This rule has been split into the following rules:
architecture_003¶
This rule checks for a blank lines or comments above the architecture declaration.
Refer to Configuring Previous Line Rules for more information.
Violation
library ieee;
architecture rtl of fifo is
Fix
library ieee;
architecture rtl of fifo is
architecture_004¶
This rule checks the proper case of the architecture keyword in the architecture declaration.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
ARCHITECTURE rtl of fifo is
architecture rtl of fifo is
architecture_005¶
This rule checks the of keyword is on the same line as the architecture keyword.
Violation
architecture rtl
of fifo is
Fix
architecture rtl of
fifo is
architecture_006¶
This rule checks the is keyword is on the same line as the architecture keyword.
Violation
architecture rtl of fifo
is
architecture rtl of fifo
Fix
architecture rtl of fifo is
architecture rtl of fifo is
architecture_007¶
This rule checks for spaces before the begin keyword.
Violation
architecture rtl of fifo is
begin
Fix
architecture rtl of fifo is
begin
architecture_008¶
This rule checks for spaces before the end architecture keywords.
Violation
architecture rtl of fifo is
begin
end architecture
Fix
architecture rtl of fifo is
begin
end architecture
architecture_009¶
This rule checks the end keyword has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
END architecture;
End architecture;
Fix
end architecture;
end architecture;
architecture_010¶
This rule checks for the keyword architecture in the end architecture statement. It is clearer to the reader to state what is ending.
Refer to Configuring Optional Items for more information.
Violation
end architecture_name;
Fix
end architecture architecture_name;
architecture_011¶
This rule checks the architecture name case in the end architecture statement.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
end architecture ARCHITECTURE_NAME;
Fix
end architecture architecture_name;
architecture_012¶
This rule checks for a single space between end and architecture keywords.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
end architecture architecture_name;
Fix
end architecture architecture_name;
architecture_013¶
This rule checks the case of the architecture name in the architecture declaration.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
architecture RTL of fifo is
Fix
architecture rtl of fifo is
architecture_014¶
This rule checks the case of the entity name in the architecture declaration.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
architecture rtl of FIFO is
Fix
architecture rtl of fifo is
architecture_015¶
This rule checks for blank lines below the architecture declaration.
Refer to Configuring Blank Lines for more information.
Violation
architecture rtl of fifo is
signal wr_en : std_logic;
begin
Fix
architecture rtl of fifo is
signal wr_en : std_logic;
begin
architecture_016¶
This rule checks for blank lines above the begin keyword.
Refer to Configuring Blank Lines for more information.
Violation
architecture rtl of fifo is
signal wr_en : std_logic;
begin
Fix
architecture rtl of fifo is
signal wr_en : std_logic;
begin
architecture_017¶
This rule checks for a blank line below the begin keyword.
Refer to Configuring Blank Lines for more information.
Violation
begin
wr_en <= '0';
Fix
begin
wr_en <= '0';
architecture_018¶
This rule checks for blank lines or comments above the end architecture declaration.
Refer to Configuring Blank Lines for more information.
Violation
rd_en <= '1';
end architecture RTL;
Fix
rd_en <= '1';
end architecture RTL;
architecture_019¶
This rule checks the proper case of the of keyword in the architecture declaration.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
architecture rtl OF fifo is
Fix
architecture rtl of fifo is
architecture_020¶
This rule checks the proper case of the is keyword in the architecture declaration.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
architecture rtl of fifo IS
Fix
architecture rtl of fifo is
architecture_021¶
This rule checks the proper case of the begin keyword.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
architecture rtl of fifo is
BEGIN
Fix
architecture rtl of fifo is
begin
architecture_022¶
This rule checks for a single space before the entity name in the end architecture declaration.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
end architecture fifo;
Fix
end architecture fifo;
architecture_024¶
This rule checks for the architecture name in the end architecture statement. It is clearer to the reader to state which architecture the end statement is closing.
Refer to Configuring Optional Items for more information.
Violation
end architecture;
Fix
end architecture architecture_name;
architecture_025¶
This rule checks for valid names for the architecture. Typical architecture names are: RTL, EMPTY, and BEHAVE. This rule allows the user to restrict what can be used for an architecture name.
Note
This rule is disabled by default. You can enable and configure the names using the following configuration.
---
rule :
architecture_025 :
disable : False
names :
- rtl
- empty
- behave
Violation
architecture some_invalid_arch_name of entity1 is
Fix
The user is required to decide which is the correct architecture name.
architecture_026¶
This rule checks the colons are in the same column for all declarations in the architecture declarative part.
Refer to Configuring Keyword Alignment Rules for information on changing the configurations.
Violation
architecture rtl of my_entity is
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_period : time;
begin
Fix
architecture rtl of my_entity is
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_period : time;
begin
architecture_027¶
This rule checks the alignment of inline comments in the architecture declarative part.
Refer to Configuring Keyword Alignment Rules for information on changing the configurations.
Violation
architecture rtl of my_entity is
signal wr_en : std_logic; -- Comment 1
signal rd_en : std_logic; -- Comment 2
constant c_period : time; -- Comment 3
begin
Fix
architecture rtl of my_entity is
signal wr_en : std_logic; -- Comment 1
signal rd_en : std_logic; -- Comment 2
constant c_period : time; -- Comment 3
begin
architecture_028¶
This rule checks the architecture keyword in the end architecture has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
end ARCHITECTURE;
end Architecture;
Fix
end architecture;
end architecture;
architecture_029¶
This rule checks for alignment of names in alias, attribute, type, subtype, constant, signal, variable and file declarations in the architecture declarative region.
Refer to Configuring Identifier Alignment Rules for more information.
Violation
signal sig1 : std_logic;
file some_file :
variable v_var1 : std_logic;
type t_myType : std_logic;
Fix
signal sig1 : std_logic;
file some_file :
variable v_var1 : std_logic;
type t_myType : std_logic;
architecture_030¶
This rule checks for a single space between architecture and the name.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
architecture rtl of fifo is
Fix
architecture rtl of fifo is
architecture_031¶
This rule checks for a single space between the name and the of keyword.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
architecture rtl of fifo is
Fix
architecture rtl of fifo is
architecture_032¶
This rule checks for a single space between the of keyword and the entity_name.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
architecture rtl of fifo is
Fix
architecture rtl of fifo is
architecture_033¶
This rule checks for a single space between the entity_name and the is keyword.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
architecture rtl of fifo is
Fix
architecture rtl of fifo is
architecture_200¶
This rule checks for a blank line below the end architecture statement.
Refer to Configuring Blank Lines for more information.
Violation
end architecture;
library ieee;
Fix
end architecture;
library ieee;
architecture_400¶
This rule checks the colons are in the same column for all attribute specifications.
Refer to Configuring Keyword Alignment Rules for information on changing the configurations.
Violation
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
Fix
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
architecture_600¶
This rule checks for consistent capitalization of generic names in an architecture body.
Violation
entity FIFO is
generic (
G_WIDTH : natural := 16
);
end entity fifo;
architecture rtl of fifo is
signal w_data : std_logic_vector(g_width - 1 downto 0);
begin
output <= large_data(g_width - 1 downto 0);
end architecture rtl;
Fix
entity FIFO is
generic (
G_WIDTH : natural := 16
);
end entity fifo;
architecture rtl of fifo is
signal w_data : std_logic_vector(G_WIDTH - 1 downto 0);
begin
output <= large_data(G_WIDTH - 1 downto 0);
end architecture rtl;
architecture_601¶
This rule checks for consistent capitalization of port names in an architecture body.
Violation
entity FIFO is
port (
I_DATA : in std_logic_vector(31 downto 0)
);
end entity fifo;
architecture rtl of fifo is
begin
register <= i_data;
end architecture rtl;
Fix
entity FIFO is
port (
I_DATA : in std_logic_vector(31 downto 0)
);
end entity fifo;
architecture rtl of fifo is
begin
register <= I_DATA;
end architecture rtl;