Variable Rules¶
variable_001¶
This rule checks the indent of variable declarations.
Violation
proc : process () is
variable count : integer;
variable counter : integer;
begin
Fix
proc : process () is
variable count : integer;
variable counter : integer;
begin
variable_002¶
This rule checks the variable keyword has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
VARIABLE count : integer;
Fix
variable count : integer;
variable_003¶
This rule was deprecated and replaced with rules:
variable_004¶
This rule checks the variable name has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
variable COUNT : integer;
Fix
variable count : integer;
variable_005¶
This rule checks there is a single space after the colon.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
variable count :integer;
variable counter : integer;
Fix
variable count : integer;
variable counter : integer;
variable_006¶
This rule checks for at least a single space before the colon.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
variable count: integer;
variable counter : integer;
Fix
variable count : integer;
variable counter : integer;
variable_007¶
This rule checks for default assignments in variable declarations.
Violation
variable count : integer := 32;
Fix
variable count : integer;
variable_010¶
The function of this rule has been superceeded by the following rules:
- ieee_500
- subtype_002
- type_014
variable_011¶
This rule checks for consistent capitalization of variable names.
Violation
architecture rtl of entity1 is
shared variable var1 : std_logic;
shared variable var2 : std_logic;
begin
proc_name : process () is
variable var3 : std_logic;
variable var4 : std_logic;
begin
Var1 <= '0';
if (VAR2 = '0') then
vaR3 <= '1';
elisif (var2 = '1') then
VAR4 <= '0';
end if;
end process proc_name;
end architecture rtl;
Fix
proc_name : process () is
variable var1 : std_logic;
variable var2 : std_logic;
variable var3 : std_logic;
variable var4 : std_logic;
begin
var1 <= '0';
if (var2 = '0') then
var3 <= '1';
elisif (var2 = '1') then
var4 <= '0';
end if;
end process proc_name;
variable_012¶
This rule checks for valid prefixes on variable identifiers. The default variable prefix is v_.
Refer to Configuring Prefix and Suffix Rules for more information.
Violation
variable my_var : natural;
Fix
variable v_my_var : natural;
variable_017¶
This rule checks the structure of variable constraints.
Refer to Configuring Multiline Constraint Rules for more information.
Note
The indenting of multiline variable constraints is handled by the rule variable_400.
Violation
variable v_element : my_record(element1(7 downto 0), element2(3 downto 0));
Fix
variable v_element : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
variable_400¶
This rule checks alignment of multiline constraints in variable declarations.
Refer to Configuring Multiline Indent Rules for more information.
Violation
variable v_element : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
Fix
variable v_element : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
variable_600¶
This rule checks for valid suffix on variable identifiers. The default variable suffix is _v.
Refer to Configuring Prefix and Suffix Rules for more information.
Violation
variable my_var : natural;
Fix
variable my_var_v : natural;