Component Rules¶
component_001¶
This rule checks the indentation of the component keyword.
Violation
architecture RTL of FIFO is
begin
component FIFO is
component RAM is
Fix
architecture RTL of FIFO is
begin
component FIFO is
component RAM is
component_002¶
This rule checks for a single space after the component keyword.
Violation
component FIFO is
Fix
component FIFO is
component_003¶
This rule checks for a blank line above the component declaration.
Violation
end component FIFO;
component RAM is
Fix
end component FIFO;
component RAM is
component_004¶
This rule checks the component keyword has proper case.
Note
The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
COMPONENT FIFO is
Component FIFO is
Fix
component FIFO is
component FIFO is
component_005¶
This rule checks the is keyword is on the same line as the component keyword.
Violation
component FIFO
component FIFO
is
Fix
component FIFO is
component FIFO is
component_006¶
This rule checks the is keyword has proper case.
Note
The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
componet FIFO IS
componet FIFO Is
Fix
component FIFO is
component FIFO is
component_007¶
This rule checks for a single space before the is keyword.
Violation
component FIFO is
Fix
component FIFO is
component_008¶
This rule checks the component name has proper case in the component declaration.
Note
The default is uppercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
component fifo is
Fix
component FIFO is
component_009¶
This rule checks the indent of the end component keywords.
Violation
OVERFLOW : std_logic
);
end component FIFO;
Fix
OVERFLOW : std_logic
);
end component FIFO;
component_010¶
This rule checks the end keyword has proper case.
Note
The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
END component FIFO;
Fix
end component FIFO;
component_011¶
This rule checks for single space after the end keyword.
Violation
end component FIFO;
Fix
end component FIFO;
component_012¶
This rule checks the proper case of the component name in the end component line.
Note
The default is uppercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
end component fifo;
Fix
end component FIFO;
component_013¶
This rule checks for a single space after the component keyword in the end component line.
Violation
end component FIFO;
Fix
end component FIFO;
component_014¶
This rule checks the component keyword in the end component line has proper case.
Note
The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
end COMPONENT FIFO;
Fix
end component FIFO;
component_015¶
This rule checks for the component keyword in the end component line.
Violation
end FIFO;
end;
Fix
end component FIFO;
end component;
component_016¶
This rule checks for blank lines above the end component line.
Violation
OVERFLOW : std_logic
);
end component FIFO;
Fix
OVERFLOW : std_logic
);
end component FIFO;
component_017¶
This rule checks the alignment of the : in port declarations.
Violation
RD_EN : in std_logic;
WR_EN : in std_logic;
OVERFLOW : out std_logic;
Fix
RD_EN : in std_logic;
WR_EN : in std_logic;
OVERFLOW : out std_logic;
component_018¶
This rule checks for a blank line below the end component line.
Violation
end component FIFO;
signal rd_en : std_logic;
Fix
end component FIFO;
signal rd_en : std_logic;
component_019¶
This rule checks for comments at the end of the port and generic assignments in component declarations. These comments represent additional maintainence. They will be out of sync with the entity at some point. Refer to the entity for port types, port directions and purpose.
Violation
WR_EN : in std_logic; -- Enables write to RAM
RD_EN : out std_logic; -- Enable reads from RAM
Fix
WR_EN : in std_logic;
RD_EN : out std_logic;
component_020¶
This rule checks the comments at the end of the port and generic assignments in component declarations are aligned. This rule is useful if component_019 is disabled.
Violation
WR_EN : in std_logic; -- Enables write to RAM
RD_EN : out std_logic; -- Enable reads from RAM
Fix
WR_EN : in std_logic; -- Enables write to RAM
RD_EN : out std_logic; -- Enable reads from RAM