Port Map Rules

port_map_001

phase_6 error case case_keyword

This rule checks the port map keywords have proper case.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

PORT MAP (

Fix

port map (

port_map_002

phase_6 error case case_name

This rule checks the port names have proper case.

Refer to Configuring Uppercase and Lowercase Rules for more information.

Violation

port map (
  wr_en              => wr_en,
  rd_en              => rd_en,
  OVERFLOW           => overflow,
  underflow(c_index) => underflow
);

Fix

port map (
  wr_en              => wr_en,
  rd_en              => rd_en,
  overflow           => overflow,
  underflow(c_index) => underflow
);

port_map_003

phase_1 error structure

This rule checks the “(” character is on the same line as the port map keywords.

Violation

port map
(
  WR_EN    => WR_EN,
  RD_EN    => RD_EN,
  OVERFLOW => OVERFLOW
);

Fix

Use explicit port mapping.

port map (
  WR_EN    => WR_EN,
  RD_EN    => RD_EN,
  OVERFLOW => OVERFLOW
);

port_map_004

phase_1 error structure

This rule checks the location of the closing “)” character for the port map.

The default location is on a line by itself.

Refer to Configuring Move Token Rules for more information.

Violation

port map (
  WR_EN => wr_en);

Fix

port map (
  WR_EN => wr_en
);

port_map_005

phase_1 error structure

This rule checks for a port assignment on the same line as the port map keyword.

Violation

port map (WR_EN    => wr_en,
  RD_EN    => rd_en,
  OVERFLOW => overflow
);

Fix

port map (
  WR_EN    => wr_en,
  RD_EN    => rd_en,
  OVERFLOW => overflow
);

port_map_007

phase_2 error whitespace

This rule checks for a single space after the => operator in port maps.

Violation

U_FIFO : FIFO
  port map (
    WR_EN    =>   wr_en,
    RD_EN    =>rd_en,
    OVERFLOW =>     overflow
  );

Fix

U_FIFO : FIFO
  port map (
    WR_EN    => wr_en,
    RD_EN    => rd_en,
    OVERFLOW => overflow
  );

port_map_008

phase_1 error structure

This rule checks for positional ports. Positional ports are subject to problems when the position of the underlying component changes.

Violation

port map (
  WR_EN, RD_EN, OVERFLOW
);

Fix

Use explicit port mapping.

port map (
  WR_EN    => WR_EN,
  RD_EN    => RD_EN,
  OVERFLOW => OVERFLOW
);

port_map_009

phase_1 error structure

This rule checks multiple port assignments on the same line.

Violation

port map (
  WR_EN => w_wr_en, RD_EN => w_rd_en,
  OVERFLOW => w_overflow
);

Fix

port map (
  WR_EN => w_wr_en,
  RD_EN => w_rd_en,
  OVERFLOW => w_overflow
);