Signal Rules¶
signal_001¶
This rule checks the indent of signal declarations.
Violation
architecture rtl of fifo is
signal wr_en : std_logic;
signal rd_en : std_logic;
begin
Fix
architecture rtl of fifo is
signal wr_en : std_logic;
signal rd_en : std_logic;
begin
signal_002¶
This rule checks the signal keyword has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
SIGNAL wr_en : std_logic;
Fix
signal wr_en : std_logic;
signal_003¶
This rule was depricated and replaced with rules:
signal_004¶
This rule checks the signal name has proper case.
Refer to Configuring Uppercase and Lowercase Rules for more information.
Violation
signal WR_EN : std_logic;
Fix
signal wr_en : std_logic;
signal_005¶
This rule checks for a single space after the colon.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
signal wr_en : std_logic;
signal rd_en :std_logic;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal_006¶
This rule checks for at least a single space before the colon.
Refer to Configuring Whitespace Rules for options on changing the number of whitespaces..
Violation
signal wr_en: std_logic;
signal rd_en : std_logic;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal_007¶
This rule checks for default assignments in signal declarations.
Note
This rule requires the user to remove the default assignments.
Violation
signal wr_en : std_logic := '0';
Fix
signal wr_en : std_logic;
signal_008¶
This rule checks for valid prefixes on signal identifiers. Default signal prefix is s_.
Refer to Configuring Prefix and Suffix Rules for more information.
Violation
signal wr_en : std_logic;
signal rd_en : std_logic;
Fix
signal s_wr_en : std_logic;
signal s_rd_en : std_logic;
signal_010¶
The function of this rule has been moved to rule ieee_500.
signal_011¶
The function of this rule has been superceeded by the following rules:
- ieee_500
- subtype_002
- type_014
signal_012¶
This rule checks multiple signal declarations on a single line are column aligned.
Note
This rule will only cover two signals on a single line.
Violation
signal wr_en, wr_en_f : std_logic;
signal rd_en_f, rd_en : std_logic;
signal chip_select, chip_select_f : t_user_defined_type;
Fix
signal wr_en, wr_en_f : std_logic;
signal rd_en_f, rd_en : std_logic;
signal chip_select, chip_select_f : t_user_defined_type;
signal_014¶
This rule checks for consistent capitalization of signal names.
Violation
architecture rtl of entity1 is
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
proc_name : process (siG2) is
begin
siG1 <= '0';
if (SIG2 = '0') then
sIg1 <= '1';
elisif (SiG2 = '1') then
SIg1 <= '0';
end if;
end process proc_name;
end architecture rtl;
Fix
architecture rtl of entity1 is
signal sig1 : std_logic;
signal sig2 : std_logic;
proc_name : process (sig2) is
begin
sig1 <= '0';
if (sig2 = '0') then
sig1 <= '1';
elisif (sig2 = '1') then
sig1 <= '0';
end if;
end process proc_name;
end architecture rtl;
signal_015¶
This rule checks for multiple signal names defined in a single signal declaration. By default, this rule will only flag more than two signal declarations.
Refer to Configuring Number of Signals in Signal Declaration for more information.
Violation
signal sig1, sig2
sig3, sig4,
sig5
: std_logic;
Fix
signal sig1 : std_logic;
signal sig2 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal_017¶
This rule checks the structure of signal constraints.
Refer to Configuring Multiline Constraint Rules for more information.
Note
The indenting of multiline signal constraints is handled by the rule signal_400.
Violation
signal sig_a : my_record(element1(7 downto 0), element2(3 downto 0));
Fix
signal sig_a : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
signal_400¶
This rule checks alignment of multiline constraints in signal declarations.
Refer to Configuring Multiline Indent Rules for more information.
Violation
signal sig_a : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
Fix
signal sig_a : my_record(
element1(7 downto 0),
element2(3 downto 0)
);
signal_600¶
This rule checks for valid suffixes on signal identifiers. Default signal suffix is _s.
Refer to Configuring Prefix and Suffix Rules for more information.
Violation
signal wr_en : std_logic;
signal rd_en : std_logic;
Fix
signal wr_en_s : std_logic;
signal rd_en_s : std_logic;