Signal Rules¶
signal_001¶
This rule checks the indent of signal declarations.
Violation
architecture RTL of FIFO is
signal wr_en : std_logic;
signal rd_en : std_logic;
begin
Fix
architecture RTL of FIFO is
signal wr_en : std_logic;
signal rd_en : std_logic;
begin
signal_002¶
This rule checks the signal keyword has proper case.
Note
The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
SIGNAL wr_en : std_logic;
Fix
signal wr_en : std_logic;
signal_003¶
This rule checks for spaces after the signal keyword.
Violation
signal wr_en : std_logic;
Fix
signal wr_en : std_logic;
Note
The number of spaces after the signal keyword is configurable. Use the following YAML file example to change the default number of spaces.
- rule:
- signal_003:
- spaces: 3
signal_004¶
This rule checks the signal name has proper case.
Note
The default is lowercase.
Violation
signal WR_EN : std_logic;
Fix
signal wr_en : std_logic;
signal_005¶
This rule checks for a single space after the colon.
Violation
signal wr_en : std_logic;
signal rd_en :std_logic;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal_006¶
This rule checks for at least a single space before the colon.
Violation
signal wr_en: std_logic;
signal rd_en : std_logic;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal_007¶
This rule checks for default assignments in signal declarations.
Violation
signal wr_en : std_logic := '0';
Fix
signal wr_en : std_logic;
signal_008¶
This rule checks for valid prefixes on signal identifiers.
Note
Default signal prefix is “s_”.
Refer to the section Configuring Prefix and Suffix Rules for information on changing the allowed prefixes.
Violation
signal wr_en : std_logic;
signal rd_en : std_logic;
Fix
signal s_wr_en : std_logic;
signal s_rd_en : std_logic;
signal_009¶
This rule has be renumbered signal_013.
signal_010¶
This rule checks the signal type has proper case if it is a VHDL keyword.
Note
This rule is disabled by default. The default is lowercase.
Refer to the section Configuring Uppercase and Lowercase Rules for information on changing the default case.
Violation
signal wr_en : STD_LOGIC;
signal rd_en : Std_logic;
signal cs_f : t_User_Defined_Type;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal cs_f : t_User_Defined_Type;
signal_011¶
This rule checks the signal type is lowercase.
Violation
signal wr_en : STD_LOGIC;
signal rd_en : Std_logic;
signal cs_f : t_User_Defined_Type;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal cs_f : t_user_defined_type;
signal_012¶
This rule checks multiple signal assignments on a single line are column aligned.
Note
The :’s will be aligned with rule signal_009. This rule will only cover two signals on a single line.
Violation
signal wr_en, wr_en_f : std_logic;
signal rd_en_f, rd_en : std_logic;
signal chip_select, chip_select_f : t_user_defined_type;
Fix
signal wr_en, wr_en_f : std_logic;
signal rd_en_f, rd_en : std_logic;
signal chip_select, chip_select_f : t_user_defined_type;
signal_013¶
This rule checks the colons are aligned for all signals in the architecture declarative region.
Violation
signal wr_en : std_logic;
signal rd_en : std_logic;
Fix
signal wr_en : std_logic;
signal rd_en : std_logic;
signal_014¶
This rule checks for consistent capitalization of signal names.
Violation
architecture RTL of ENTITY1 is
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
PROC_NAME : process (siG2) is
begin
siG1 <= '0';
if (SIG2 = '0') then
sIg1 <= '1';
elisif (SiG2 = '1') then
SIg1 <= '0';
end if;
end process PROC_NAME;
end architecture RTL;
Fix
architecture RTL of ENTITY1 is
signal sig1 : std_logic;
signal sig2 : std_logic;
PROC_NAME : process (sig2) is
begin
sig1 <= '0';
if (sig2 = '0') then
sig1 <= '1';
elisif (sig2 = '1') then
sig1 <= '0';
end if;
end process PROC_NAME;
end architecture RTL;
signal_015¶
This rule checks for multiple signal names defined in a single signal declaration.
Note
By default, this rule will only flag more than two signal declarations. Refer to the section Configuring Number of Signals in Signal Declaration for information on changing the default.
Violation
signal sig1, sig2
sig3, sig4,
sig5
: std_logic;
Fix
signal sig1 : std_logic;
signal sig2 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal_016¶
This rule checks the signal declaration is on a single line.
Violation
signal sig1
: std_logic;
signal sig2 :
std_logic;
Fix
signal sig1 : std_logic;
signal sig2 : std_logic;